1. Field of the Invention
The present invention relates to a method of trench isolation and a method for manufacturing a non-volatile memory device using the same. More particularly, the present invention relates to a method of shallow trench isolation capable of preventing a semiconductor device from deteriorating during formation of a trench and simplifying fabricating processes of the semiconductor device, and to a method for manufacturing a non-volatile memory device using the same.
2. Description of the Related Art
In fabrication of highly-integrated memory devices, integration degree of a memory cell is generally determined according to layout of the memory cell and scalability of the layout proportional to reduction of critical dimension (CD) of the memory cell. As the CD is reduced below sub-micron, the scalability of the layout is restricted by resolution of the semiconductor fabricating process and alignment tolerances of masks for the design. The alignment of the mask is restricted by technologies for positioning the mask over a wafer and for consistently forming a pattern on the mask. When the alignment tolerances are accumulated, the layout of the memory cell may be mis-aligned. Accordingly, to reduce the alignment tolerances in design of the memory cell, it is preferable to use a smallest number of alignment critical masks.
Most highly-integrated memory cells are designed for isolating cells arrayed in a column direction in a cell array. To increase the integration degree of the memory cell, it is preferable to minimize dimensions of isolation structures. However, the dimensions of the isolation structures are restricted by processes for forming the isolation structure and by structures of the memory cell array.
Typically, the isolation structure is formed through a thermal field oxidation process, for example, such as a local oxidation of silicon (LOCOS). In accordance with the LOCOS, an oxide layer and a nitride layer are formed on a silicon substrate. The nitride layer is patterned to form a nitride layer pattern. The silicon substrate is partially oxidized using the nitride layer pattern as an oxidation preventing mask to form a field oxide layer on the substrate. In this process, oxygen penetrates from a lower portion of the nitride layer pattern into a side surface of the oxide layer so that a bird's beak is formed on an end portion of the field oxide layer. The field oxide layer is extended toward an active region by a length of the bird's beak. As a result, a width of the active region is reduced, thereby deteriorating electrical characteristics of the semiconductor device.
To solve the above problem caused by the bird's beak, a method of a shallow trench isolation (STI) is disclosed. In accordance with the STI method, a silicon substrate is etched to form a trench in the silicon substrate. An oxide layer is formed on the substrate to fill the trench with the oxide layer. The oxide layer is etched through an etch-back process or a chemical mechanical polishing (CMP) process to form a field oxide layer in the trench.
The LOCOS process and the STI process include forming the mask and forming the field oxide layer for defining the active region. After the isolation structure is formed on the substrate, processes for forming the memory cells using masks are performed. Since the alignment tolerances accompanying the formation of the isolation structure and the layout of the memory cell are combined, the mis-alignment disadvantageously occurs on the semiconductor device.
To prevent the mis-alignment, a conventional method for forming an isolation structure according to the LOCOS process on a floating gate through a self-align process in a non-volatile memory device is disclosed. A conventional method for forming an isolation structure according to the STI process on a floating gate through a self-align process is also disclosed in U.S. Pat. Publication No. 6,013,551. According to the above conventional methods, the floating gate used for storing an electric charge and the gate region are defined using one mask so that the isolation structure is provided between the active region and the floating gate through the self-align process.
When data is inputted into the non-volatile memory device, the data in the non-volatile memory device is generally maintained as it is regardless of lapse of time. Recently, there is a high demand for a flash memory device into which a data is electrically input and from which a data is electrically output. A memory cell of the flash memory device storing the data includes a floating gate formed on a tunnel oxide layer that is formed on a silicon substrate, and a control gate formed on an insulating interlayer that is formed on the floating gate. An input/output of the data in the flash memory device is performed through providing/extracting the electric charge into/from the floating gate by applying a voltage to the control gate and the substrate. Here, the insulating interlayer keeps the electric charge in the floating gate and transmits the voltage applied to the control gate into the floating gate.
FIGS. 1A to 1G are perspective views illustrating a conventional method for manufacturing a flash memory device using a STI process.
Referring to FIG. 1A, an oxide layer 11 is formed on a silicon substrate 10. A first polysilicon layer 13 and a nitride layer 15 are successively formed on the oxide layer 11. Here, the oxide layer 11 serves as a gate oxide layer of a flash memory cell, that is, a tunnel oxide layer. The first polysilicon layer 13 serves as a floating gate. The nitride layer 15 serves as a polishing stop layer.
Referring to FIG. 1B, the nitride layer 15, the first polysilicon layer 13 and the oxide layer 11 are etched using a photoresist pattern (not shown) as a mask to form a nitride layer pattern 16, a first polysilicon layer pattern 14 and an oxide layer pattern 12. An upper portion of the substrate 10 adjacent to the first polysilicon pattern 14 is etched using the photoresist pattern as a mask to form a trench 18. An active region is defined on the substrate 10, and a floating gate is simultaneously formed on the substrate 10 using one mask.
Referring to FIG. 1C, to cure damage of the silicon substrate 10 caused by high energy of ion impact during the etching process and to suppress leakage current at the vicinity of the trench 18, a portion exposed through the trench 18 is thermally treated under oxygen atmosphere. A thermal oxide layer 20 is formed on a bottom and a sidewall of the trench 18 by reacting oxygen with silicon. Here, the thermal treating process is performed at a temperature of about 820° C. for about 3 hours to about 3.5 hours. An inner wall of the trench 18 is annealed at a temperature of about 850° C. under dinitrogen monoxide (N2O) or nitrogen monoxide (NO) atmosphere.
FIG. 2 is an enlarged sectional view of the portion labeled ‘D’ in FIG. 1C. With reference to FIG. 2, oxygen penetrates from the lower portion of the first polysilicon pattern 14 into the side surface of the oxide layer pattern 12 during the oxidation process so that a bird's beak A is formed on the first polysilicon pattern 14. Further, the oxide layer pattern 12 is expanded during the oxidation process. However, the expansion of the oxide layer pattern 12 is restricted at interface edges between the first polysilicon layer pattern 14 and the oxide layer pattern 12 and between the silicon substrate 10 and the oxide layer pattern 12. Thus, stresses caused from the expansion of the oxide layer pattern 14 are concentrated on the interface edges so that oxygen is slowly diffused, thereby suppressing the oxidation (see ‘B’ portion of FIG. 2). As a result, a bottom edge of the first polysilicon layer pattern 14 is bent upwardly so that the sidewall of the first polysilicon pattern 14 has a positive slope (see ‘C’ portion of FIG. 2). Here, the positive slope represents that the sidewall of the first polysilicon pattern 14 may be eroded by an etchant. On the contrary, since penetration of oxygen into an upper portion of the first polysilicon pattern 14 is restricted by the nitride layer pattern 16, the upper portion of the first polysilicon pattern 14 has a negative slope.
Referring again to FIG. 1C, a medium temperature oxide layer 30 is formed on the trench 18 and the nitride layer pattern 16 through a process using a silane (SiH4) gas and a dinitrogen monoxide (N2O) gas at a temperature of about 750° C. for about 4 hours. The medium temperature oxide layer 30 prevents the trench 18 and the nitride layer pattern 16 from being damaged by plasma during a gap filling process.
Referring to FIG. 1D, an oxide layer 21 is formed on the resultant structure through a chemical vapor deposition (CVD) process to fill the trench 18 with the oxide layer 21.
Referring to FIG. 1E, the oxide layer 21 is removed to expose the upper surface of the first polysilicon layer pattern 14 through the CMP process to form a field oxide layer 22 defining the active region in the trench 18. A second polysilicon layer (not shown) used as a floating gate is formed on the first polysilicon layer pattern 14 and the field oxide layer 22. The second polysilicon layer is contacted with the first polysilicon layer pattern 14 to broaden an area of dielectric layer 26 (see FIG. 1F).
Referring to FIG. 1F, the second polysilicon layer on the field oxide layer 22 is patterned through a photolithography process to form a second polysilicon layer pattern 24 on the first polysilicon layer pattern 14. The dielectric layer 26 and a control gate layer 28 are formed on the resultant structure. The control gate layer 28 has a stacked polycide structure having a doped polysilicon layer and a tungsten silicide layer.
Referring to FIG. 1G, the control gate layer 28 is patterned through the photo lithography process. The dielectric layer 26, the second polysilicon layer pattern 24 and the first polysilicon layer pattern 14 are dry etched. A stacked gate structure that includes the floating gate 25 having the first and second polysilicon layer patterns 14 and 24, and the control gate 28, is formed on the memory cell region.
However, as shown in the ‘E’ portion of FIG. 1F, since the lower portion of the sidewall of the first polysilicon layer pattern 14 has the positive slope, a portion of the first polysilicon layer pattern 14 being masked with the field oxide layer 22 may be not etched during the dry etching process, but rather it may remain. The residue of the first polysilicon layer pattern 14 is formed in a line at an intersection of the first polysilicon layer pattern 14, the field oxide layer 22 and the substrate 10 along a surface boundary between the field oxide layer 22 and the active region. The residue of the first polysilicon layer pattern 14 may serve as a bridge connected between the adjacent floating gates 25, thereby inducing electrical failure of the semiconductor device.
Additionally, a time greater than or equal to about seven hours may be required for forming the thermal oxide layer 20 and the medium temperature oxide layer 30. Furthermore, the substrate may be transferred between various chambers to perform the above processes. Therefore, the semiconductor fabricating processes may be complicated and also the cost for fabricating the semiconductor device may be high.